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max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 general description the max5380/max5381/max5382 are low-cost, 8-bit digital-to-analog converters (dacs) in miniature 5-pin sot23 packages, with a simple 2-wire serial interface that allows communication with multiple devices. the max5380 has an internal +2v reference and operates from a +2.7v to +3.6v supply. the max5381 has an internal +4v reference and operates from a +4.5v to +5.5v supply. the max5382 operates over the full +2.7v to +5.5v supply range and has an internal refer- ence equal to 0.9 x v dd . the fast-mode i 2 c-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnect complexity in many applications. each device is available with one of four factory-preset addresses (see selector guide ). these dacs also include an output buffer, a low-power shutdown mode, and a power-on reset that ensures the dac outputs are at zero when power is initially applied. in shutdown mode, supply current is reduced to less than 1? and the output is pulled down to gnd with a 10k ? resistor. applications automatic tuning (vco) power-amplifier bias control programmable threshold levels automatic gain control automatic offset adjustment features 8-bit accuracy in a miniature 5-pin sot23 wide +2.7v to +5.5v supply range (max5382) low 230a max supply current 1a shutdown mode buffered output drives resistive loads low-glitch power-on reset to zero dac output fast i 2 c-compatible serial interface <5% full-scale error (max5382) <1lsb max inl/dnl px.1/scl +2.7v to +5.5v px.0/sda gnd c v dd scl sda out gnd v dd max5382 typical operating circuit 19-1641; rev 1; 1/01 ordering information i 2 c is a trademark of philips corp. selector guide part max5380 _euk-t max5381 _euk-t max5382 _euk-t -40? to +85? -40? to +85? -40? to +85? temp. range pin-package 5 sot23 5 sot23 5 sot23 part max5380 leuk max5380meuk max5380neuk 0x64 0x62 0x60 address reference (v) +2.0 +2.0 +2.0 max5380peuk 0x66 +2.0 max5381 leuk 0x60 +4.0 max5381meuk 0x62 +4.0 max5381neuk 0x64 +4.0 MAX5381PEUK 0x66 +4.0 max5382meuk 0x62 0.9 x v dd max5382neuk 0x64 0.9 x v dd max5382peuk 0x66 0.9 x v dd max5382 leuk 0x60 0.9 x v dd top mark admn admz adfn admp admv adnb adml adnd adnj adnt admx adnh gnd sda v dd 15 scl out max5380 max5381 max5382 sot23-5 top view 2 34 pin configuration ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +3.6v (max5380), v dd = +4.5v to +5.5v (max5381), v dd = +2.7v to +5.5v (max5382); r l = 10k ? ; c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v out, scl, sda to gnd ...........................................-0.3v to +6v maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 5-pin sot23 (derate 7.1mw/? above +70?).............571mw operating temperature ranges max538_ _euk-t .............................................-40? to +85? storage temperature range .............................-65? to +150? maximum junction temperature .....................................+150? lead temperature (soldering, 10s) .................................+300? 1.8 2 2.2 max5380 max5382 max5380/max5381 max5382 max5380/max5381 max5382 max5380/max5381 offset error temperature coefficient 1 ppm/? (note 2) digital-analog glitch impulse 40 nvs wake-up time 50 ? code 127 to 128 from software shutdown parameter symbol min typ max units 3 offset error supply rejection 60 db offset error ? ?5 mv differential linearity error dnl ? lsb 10 full-scale error 5 % of ideal fs full-scale error supply rejection 50 db ?0 resolution 8 bits integral linearity error inl ? lsb full-scale error temperature coefficient ?0 0.85 x 0.9 x 0.95 x v dd v dd v dd output resistance 10 k ? voltage output slew rate 0.4 v/? output settling time 20 ? digital feedthrough 2 nvs conditions code = 255 max5382 (notes 2, 3) (note 2) guaranteed monotonic code = 255 code = 255, max5380/max5281 (note 4) max5382 v out = 0 to v dd , power-down mode (note 1) positive and negative to 1/2 lsb, 50k ? and 50pf load (note 6) code = 0, all digital inputs from 0 to v dd ppm/? 0.5 code = 255, 0 to 100? output load regulation 0.5 lsb code = 0, 0 to 100? v ref internal reference (note 5) max5381 3.6 4 4.4 static accuracy dac output dynamic performance
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +3.6v (max5380), v dd = +4.5v to +5.5v (max5381), v dd = +2.7v to +5.5v (max5382); r l = 10k ? ; c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) 250 i sink = 6ma i sink = 3ma parameter symbol min typ max units supply current i dd 1 150 230 supply voltage v dd 2.7 5.5 v input low voltage v il 0.3 x v dd v input high voltage v ih 0.7 x v dd v input hysteresis v hys 0.05 x v dd v input capacitance c in 10 pf 2.7 3.6 4.5 5.5 input leakage current i in ?0 ? pulse width of spike suppressed t sp 050 ns 0.4 output low voltage v ol 0.6 v output fall time t of 250 ns conditions shutdown mode no load, all digital inputs at 0 or v dd , code = 255 max5382 i sink = 3ma (note 7) i sink = 6ma v ih(min) to v il(max) , bus capacitance = 10pf to 400pf max5380 max5381 ? power requirements digital inputs (scl, sda) digital output (sda, open drain) data hold time t hd:dat 00.9 ? data setup time t su:dat 100 ns conditions ? 0.6 t su:sta setup time for a repeated start condition ? 0.6 t high high period of the scl clock ? 1.3 t low low period of the scl clock khz 0 400 f scl scl clock frequency ? 0.6 t hd:sta hold time repeated for a start condition ? 1.3 t buf bus free time between a stop and a start condition units min typ max symbol parameter timing characteristics (figure 3; v dd = +2.7v to +3.6v (max5380), v dd = +4.5v to +5.5v (max5381), v dd = +2.7v to +5.5v (max5382); r l = 10k ? ; c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) (note 7)
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 4 _______________________________________________________________________________________ timing characteristics (continued) (figure 3; v dd = +2.7v to +3.6v (max5380), v dd = +4.5v to +5.5v (max5381), v dd = +2.7v to +5.5v (max5382); r l = 10k ? ; c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) (note 7) note 1: guaranteed from code 5 to code 255. note 2: the offset value extrapolated from the range over which the inl is guaranteed. note 3: max5382 tested at v dd = +5v ?0%. note 4: max5380 tested at v dd = +3v ?0%, max5381 tested at v dd = 5v ?0%. note 5: actual output voltages at full scale are 255/256 x v ref . note 6: output settling time is measured by taking the code from code 5 to 255, and from code 255 to 5. note 7: guaranteed by design. rise time of both sda and scl signals t r 300 ns fall time of both sda and scl signals t f conditions 300 ns setup time for stop condition t su:sto 0.6 ? capacitive load for each bus line c b 400 pf units min typ max symbol parameter typical operating characteristics (v dd = +3.0v (max5380), v dd = +5.0v (max5381/max5382); r l = 10k ? , t a = +25?, unless otherwise noted.) -0.050 -0.075 -0.100 -0.025 0 0.025 0.050 0.075 0 100 200 50 150 250 300 integral nonlinearity vs. code max5380/1/2-01 code inl (lsb) 0 -0.10 -0.15 -0.05 -0.20 2.5 4.0 3.0 3.5 4.5 5.0 5.5 integral nonlinearity vs. supply voltage max5380/1/2-02 supply voltage (v) inl (lsb) 0 -0.10 -0.15 -0.05 -0.20 -40 20 -20 0 40 60 80 100 integral nonlinearity vs. temperature max5380/1/2-03 temperature (?) inl (lsb)
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 _______________________________________________________________________________________ 5 -0.08 -0.04 -0.02 0 0.02 0.04 0 100 200 300 50 150 250 differential nonlinearity vs. code max5380/1/2-04 code dnl (lsb) -0.06 0 -0.06 -0.08 -0.04 -0.02 -0.10 2.5 4.0 3.0 3.5 4.5 5.0 5.5 differential nonlinearity vs. supply voltage max5380/1/2-05 supply voltage (v) dnl (lsb) 0 -0.04 -0.06 -0.08 -0.02 -0.10 -40 20 -20 0 40 60 80 100 differential nonlinearity vs. temperature max5380/1/2-06 temperature ( c) dnl (lsb) -0.60 -0.30 -0.45 -0.15 0 0.15 0.30 0.45 0 100 200 300 50 150 250 total unadjusted error vs. code max5380/1/2-07 code tue (lsb) 0 -1.0 -1.5 -0.5 -2.0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 offset error vs. supply voltage max5380/1/2-08 supply voltage (v) v os (mv) 0 -1.0 -0.5 -1.5 -2.0 -40 20 -20 0 40 60 80 100 offset error vs. temperature max5380/1/2-09 temperature ( c) offset error (mv) typical operating characteristics (continued) (v dd = +3.0v (max5380), v dd = +5.0v (max5381/max5382); r l = 10k ? , t a = +25?, unless otherwise noted.) 3 1 0 -1 -2 2 -3 2.5 4.0 3.0 3.5 4.5 5.0 5.5 full-scale error vs. supply voltage max5380/1/2-10 supply voltage (v) full-scale error (lsb) 1.2 0.4 0 -0.4 -0.8 0.8 -1.2 full-scale error (%) max5381 max5380 max5382 no load 3 1 0 -1 -2 2 -3 1.2 0.4 0 -0.4 -0.8 0.8 -1.2 -40 20 -20 0 40 60 80 100 full-scale error vs. temperature max5380/1/2-11 temperature ( c) full-scale error (lsb) full-scale error (%) max5381 max5380 max5382 200 140 120 100 60 80 20 40 160 180 0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 supply current vs. supply voltage max5380/1/2-12 supply voltage (v) supply current ( a) max5381 max5380 max5382
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 6 _______________________________________________________________________________________ 160 150 145 140 135 155 130 -40 20 -20 0 40 60 80 100 supply current vs. temperature max5380/1/2-13 temperature ( c) supply current ( a) max5381 max5380 max5382 no load 160 150 145 140 135 155 130 096 32 64 128 160 192 224 256 supply current vs. code max5380/1/2-14 code supply current ( a) max5381, v dd = +5.0v no load max5382, v dd = +5.0v max5380, v dd = +5.0v max5380, v dd = +3.0v 1.0 0.4 0.2 0.6 0.8 0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 shutdown supply current vs. supply voltage max5380/1/2-15 supply voltage (v) supply current ( a) 1.0 0.6 0.4 0.2 0.8 0 -40 20 -20 0 40 60 80 100 shutdown supply current vs. temperature max5380/1/2-16 temperature ( c) supply current ( a) v dd = +5.0v v dd = +3.0v 2.0 1.5 2.5 3.0 4.0 3.5 4.5 0 0.1 0.2 02 14 36 589 710 output load regulation max5380/1/2-17 load current (ma) a: max5361/max5362, v dd = 4.5v full-scale or sourcing b: max5360, full-scale, v dd = 2.7v sinking, v dd = 5.0v sourcing c: max5360, full-scale, v dd = 2.7v sourcing d: zero code, v dd = 2.7v sinking e: zero code, v dd = 5.5v sinking v out full scale (v) v out zero code (v) a b c d e 4 s/div output voltage on power-up max5380/1/2-18 out 50mv/div v dd 2v/div typical operating characteristics (continued) (v dd = +3.0v (max5380), v dd = +5.0v (max5381/max5382); r l = 10k ? , t a = +25?, unless otherwise noted.)
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 _______________________________________________________________________________________ 7 10 s/div output voltage exiting shutdown max5380/1/2-19 out 500mv/div sda 3v/div max5380, shdn to 0x80 1 s/div output voltage entering shutdown max5380/1/2-20 out 500mv/div sda 3v/div max5380, 0x80 to shdn 1 s/div output settling from 1/4 fs to 3/4 fs max5380/1/2-21 out 0.5v/div sda 3v/div max5380 1 s/div output settling from 3/4 fs to 1/4 fs max5380/1/2-22 out 0.5v/div sda 3v/div max5380 2 s/div output settling 1lsb step up max5380/1/2-23 out 20mv/div ac-coupled sda 3v/div max5380, 0x7f to 0x80 output settling 1lsb step down max5380/1/2-24 out 20mv/div ac-coupled sda 3v/div max5380, 0x80 to 0x7f 2 s/div typical operating characteristics (continued) (v dd = +3.0v (max5380), v dd = +5.0v (max5381/max5382); r l = 10k ? , t a = +25?, unless otherwise noted.) name function 1 out dac voltage output 2 gnd ground pin 3 v dd power-supply input 4 sda serial data input 5 scl serial clock input pin description
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 8 _______________________________________________________________________________________ detailed description the max5380/max5381/max5382 voltage-output, 8-bit digital-to-analog converters (dacs) offer full 8-bit perfor- mance with less than 1lsb integral nonlinearity error and less than 1lsb differential nonlinearity error, ensur- ing monotonic performance. the devices use a simple 2-wire, fast-mode i 2 c-compatible serial interface that operates at up to 400khz. the max5380/max5381/ max5382 include an internal reference, an output buffer, and a low-current shutdown mode, which make these devices ideal for low-power, highly integrated applications (see figure 1. functional diagram) . analog section the max5380/max5381/max5382 employ a current- steering dac topology as shown in figure 2. at the core of the dac is a reference voltage-to-current converter (v/i) that generates a reference current. this current is mirrored to 255 equally weighted current sources. dac switches control the outputs of these current mirrors so that only the desired fraction of the total current-mirror currents is steered to the dac output. the current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. output voltage table 1 shows the relationship between the dac code and the analog output voltage. the 8-bit dac code is binary unipolar with 1lsb = v ref / 256. the max5380/ max5381 have a full-scale output voltage of (+2v - 1lsb) and (+4v - 1lsb), respectively, set by the internal references. the max5382 has a full-scale output volt- age of (0.9 x v dd - 1lsb). output buffer the dac voltage output is an internally buffered unity- gain follower that typically slews at ?.4v/?. the out- put can swing from 0 to full scale. with a 1/4 fs to 3/4 fs output transition, the amplifier outputs typically settle to 1/2lsb in less than 5? when loaded with 10k ? in parallel with 50pf. the buffer amplifiers are stable with any combination of resistive loads >10k ? and capaci- tive loads <50pf. v ref sw1 sw2 sw255 out figure 2. current-steering topology v dd out 10k gnd sda scl 255 8 current- steering dac data latch serial input register control logic max5380 max5381 max5382 ref figure 1. functional diagram table 1. unipolar code output voltage 0000 0001 0.9 x v dd / 256 15.6mv 7.8mv 0000 0000 0 0 0 1000 0000 0.9 x v dd / 2 +2v +1v 1111 1111 0.9 x v dd x (255 / 256) 4v x (255 / 256) 2v x (255 / 256) max5382 max5381 max5380 dac code output voltage
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 _______________________________________________________________________________________ 9 power-on reset the max5380/max5381/max5382 have a power-on reset circuit to set the dac? output to 0 when v dd is first applied or when v dd dips below 1.7v (typ). this ensures that unwanted dac output voltages will not occur immediately following a system startup, such as after a loss of power. the output glitch at startup is typi- cally less than 50mv. shutdown mode the max5380/max5381/max5382 include a software- controlled shutdown mode that reduces the supply cur- rent to <1?. all internal circuitry is disabled, and an internal 10k ? resistor is placed from out to gnd to ensure 0v at out while in shutdown. the device enters shutdown in less than 5? and exits shutdown in less than 50?. digital section serial interface the max5380/max5381/max5382 use a simple 2-wire serial interface requiring only two i/o lines (2-wire bus) of a standard microprocessor (?) port. figure 3 shows the timing diagram for signals on the 2-wire bus. the two bus lines (sda and scl) must be high when the bus is not in use. the max5380/max5381/ max5382 are receive-only devices (slaves) and must be controlled by a bus master device. figure 4 shows a typical application where up to four devices can be connected to the bus, provided they have different address settings. external pull-up resistors are not nec- essary on these lines (when driven by push-pull dri- vers), though these dacs can be used in applications where pull-up resistors are required (such as in i 2 c systems) to maintain compatibility with existing circuit- ry. the serial interface operates at scl rates up to 400khz. the sda state is allowed to change only while scl is low, with the exception of start and stop con- ditions as shown in figure 5. each transmission con- sists of a start condition sent by the bus master scl sda t low t high t f t r t hd : sta t hd : dat t hd : sta t su : dat t su : sta t buf t su : sto start condition stop condition repeated start condition start condition figure 3. 2-wire serial interface timing diagram c sda scl r s * v dd offset adjustment threshold adjustment gain adjustment *r s is optional. scl sda v dd out max5380m 2v reference scl sda v dd out max5381n 4v reference scl sda v dd out max5382p v dd reference figure 4. typical application circuit
max5380/max5381/max5382 device, followed by the max5380/max5381/max5382s preset slave address, a power-mode bit, the dac data, and finally, a stop condition (figure 6). the bus is then free for another transmission. sda? state is sampled and therefore must remain sta- ble while scl is high. data is transmitted in 8-bit bytes. nine clock cycles are required to transfer each byte to the max5380/max5381/max5382. release sda during the 9th clock cycle since the selected device acknowl- edges receipt of the byte by pulling sda low during this time. a series resistor on the sda line may be needed if the master? output is forced high while the selected device acknowledges (figure 4). slave address the max5380/max5381/max5382 are available with one of four preset slave addresses. each address option is identified by the suffix l, m, n, or p added to the part number. the address is defined as the 7msbs sent by the master after a start condition. the address options are 0x60, 0x62, 0x64, 0x66 (left justi- fied with lsb set to 0). the 8th bit, typically used to define a write or read protocol, sets the device? power mode (shdn). the device is powered-down when shdn is set to one. during a device search routine, the max5380/max5381/max5382 acknowledge both options (shdn = 0 or shdn = 1), but do not change their power state if a stop condition (or restart) is issued immediately. the second byte (dac data) must be sent/received for the device to update both power mode and dac output. dac data the 8-bit dac data is decoded as straight binary msb first with 1lsb = v ref / 256 and converted into the cor- responding analog voltage as shown in table 1. after receiving the data byte, the devices acknowledge its receipt and expect a stop condition, at which point the dac output is updated. the max5380/max5381/max5382 update the output and the power mode only if the second byte is clocked in (shdn = 0) or out (shdn = 1) of the device. when shdn = 1, the master will read all ones when clocking out a data byte. the max5380/max5381/max5382 do not drive sda except for the acknowledge bit. i 2 c compatibility the max5380/max5381/max5382 are compatible with existing i 2 c systems. scl and sda are high-imped- ance inputs; sda has an open drain that pulls the data line low during the 9th clock pulse. figure 7 shows a typical i 2 c application. the communication protocol supports standard i 2 c 8-bit communications. the gen- eral call address is ignored, and cbus formats are not supported. the devices?address is compatible with the 7-bit i 2 c addressing protocol only. no 10-bit formats low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 10 ______________________________________________________________________________________ *see ordering information. sda start condition stop condition 9 8 10 18 1 17 ack lsb msb lsb msb 0 1 1 0 a 1 0 a 2 ack shdn d7 d5 d6 d4 d2 d3 d1 d0 slave address byte dac code * a 1 a 2 0 0 l 0 1 m 1 0 n 11 p figure 6. a complete serial transmission scl sda start condition stop condition figure 5. start and stop conditions
are supported. restart protocol is supported, but an immediate stop condition is necessary to update the dac. the 8th bit of the address byte, typically used to indicate a read or write protocol, is used in the max5380/ max5381/max5382 to enter or exit shutdown mode. when max5380/max5381/max5382 are addressed in i 2 c read mode, they enter shutdown mode. applications information digital inputs and interface logic the serial 2-wire interface has logic levels defined as v il = 0.3 x v dd and v ih = 0.7 x v dd . all inputs include schmitt trigger buffers to accept slow-transition inter- faces. this means that optocouplers can interface directly to the max5380/max5381/max5382 without additional external logic. the digital inputs are compati- ble with cmos logic levels and must not be driven with voltages higher than v dd . power-supply bypassing and layout careful printed circuit board layout is important for best system performance. to reduce crosstalk and noise injection, keep analog and digital signals separate. ensure that the ground return from gnd to the supply ground is short and low impedance; a ground plane is recommended. bypass v dd with a 0.1? capacitor to ground as close as possible to the device. if the supply is excessively noisy, connect a 10 ? resistor in series with the supply and v dd and add additional capaci- tance. max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 ______________________________________________________________________________________ 11 c sda scl v dd offset adjustment threshold adjustment gain adjustment scl sda v dd out max5380l 2v reference scl sda v dd out max5381m 4v reference scl sda v dd out max5382n v dd reference figure 7. typical i 2 c application transistor count: 2910 chip information
max5380/max5381/max5382 low-cost, low-power, 8-bit dacs with 2-wire serial interface in sot23 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information sot5l.ep s

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